Programmable bias-voltage DAC

Programmable bias generation

I am developing a programmable bias-voltage DAC in Cadence Virtuoso for adjustment of the operating point of a collaborator-designed ΣΔ modulator. The design work progresses from behavioral transfer-function models to charge redistribution and transistor-level switching experiments.

The current notes document a 3-bit charge-redistribution prototype and standalone CMOS transmission-gate tests. Earlier notes include a 4-bit behavioral transfer model and background reading on cryogenic bias DACs; these are separate from the current 3-bit circuit prototype.

My contribution

I built behavioral models to examine offset, gain error, and linearity, then implemented a binary-weighted charge-redistribution DAC. The Week 5 circuit replaces ideal capacitors with n65 capacitor cells while retaining ideal switching elements for this initial DAC check.

Three-bit charge-redistribution DAC with a binary-weighted n65 capacitor array — The capacitor-array prototype from the September 26 design notes. This stage evaluates the DAC using ideal switching elements.

In parallel, I designed and simulated a CMOS transmission gate, comparing transistor sizes and examining how the switch charges a capacitor load. The work also investigates the voltage step associated with turning the switch off.

Current block-level checks

Charge-redistribution DAC

For code 100, the simulated output is 499.996 mV against a 500 mV target. This is a single-code check of the current capacitor-array prototype; it does not establish full-code accuracy for a completed DAC with transistor switches.

Simulated DAC transient response settling near 0.5 volts for code 100 — DAC output transient from the Week 5 notes. The accompanying cursor readout reports 499.996 mV.

Transmission-gate experiment

The standalone test compares a small-device configuration with a larger 1 µm NMOS / 2 µm PMOS configuration at 60 nm channel length. The larger devices improve the illustrated settling behavior. A separate hold experiment shows an approximately 3.2 mV turn-off voltage step.

Held-node waveform showing a small positive voltage step when the transmission gate turns off — Turn-off step in the standalone switch test. The plot supports examination of switching nonidealities; it is not a final DAC error specification.

Standalone transistor transmission-gate testbench with a capacitor hold load — Standalone hold-test setup from the DAC notebook. The capacitor load makes charge transfer during tracking and the voltage step at switch turn-off observable.

Input and held-node transient for the larger transmission-gate device configuration — Tracking transient for the larger-device experiment in the notes. This illustrates the role of switch sizing in charging the load; it is separate from the ideal-switch DAC output check.

These tests separate two design concerns: how quickly the load follows the input while the switch is on, and how much its voltage changes when the switch opens. Both need to be considered when replacing the prototype’s ideal switches.

The project remains at block-level design and simulation. Integrating the nonideal switches into the DAC and evaluating the resulting behavior are subsequent steps.

Selected design evidence

The circuit excerpts and transients above document my capacitor-array prototype and standalone switch experiments. They are selected from my design notes; the collaborator’s modulator implementation is outside this page’s scope.

Developing a programmable bias-voltage DAC