hw.Henan Wang

Research & engineering

Connecting device behavior
to computing hardware.

My projects span experimental devices, measurement-calibrated models, and the circuits and architectures that use them.

Detail of a cross-sectional microscopy image of the vertically aligned nanocomposite structureAu–CeO₂ vertically aligned nanocomposite

01Emerging devices · Compact modeling

Making memristor programming predictable

Measurement-calibrated compact models and programming strategies that account for nonlinear switching and post-write relaxation.

22% → 94%Targeting success within ±0.05 decade on the evaluated cell
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02Device modeling · Neuromorphic computing

Bringing measured device behavior into computing

Crossbar simulations that connect measured memristor nonidealities to synaptic updates and neural-network accuracy.

92.7%MNIST accuracy in device-aware simulation
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Three-bit charge-redistribution DAC schematic using an n65 capacitor array and ideal switching elements3-bit prototype · Charge redistribution

04Analog design · Programmable bias

Developing a programmable bias-voltage DAC

Behavioral modeling, a 3-bit charge-redistribution prototype, and separate transmission-gate experiments for a programmable bias circuit.

499.996 mVSimulated output for code 100 against a 500 mV target
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Cross-sectional microscopy of an experimental multilayer stack, with a 20 nm scale barMultilayer specimen · Cross-sectional microscopy

05Thin films · Vertical device integration

Vertical integration of selector and RRAM layers

Experimental development of vertically integrated selector–memory structures, with current work on interface quality and temperature-controlled electrical testing.

In progressInterface optimization and temperature-controlled tests
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Local transistor-level selection and output-restoration circuit schematicLocal circuit schematic · Schematic-level simulation

06MTJ p-bits · Mixed-signal circuits

Local interface circuits for MTJ p-bits

Circuit-level contributions to an ongoing collaborative project, focusing on selection circuitry, output restoration, and process-corner simulation.

5 cornersOutput transient traces: nominal, FF, SS, FS, and SF
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Simulated reference voltage versus temperature from minus 40 to 125 degrees CelsiusTemperature sweep · Pre-layout simulation

07Analog design · Voltage references

A precision bandgap voltage reference

Schematic-level design and simulation of an approximately 1.5 V reference, including temperature compensation, startup behavior, and noise analysis.

5.7 ppm/°CApproximate nominal temperature coefficient over −40 to 125 °C
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DFT project flow showing synthesis, scan insertion, and automatic test pattern generationSoCET AFTx07 · UART demonstration flow

09Design for test · Digital implementation

Scan insertion and ATPG for a UART block

Synthesis-flow and DFT contributions within the AFTx07 test-engineering team, evaluated on a UART block with four scan chains and 62 patterns.

99.18%Reported stuck-at test coverage on the UART block
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Manuscripts

Under major revision

Realizing Dual-Mode Memristor Based on Ni₀.₈Fe₀.₂-BTO/BTO/Ni₀.₈Fe₀.₂-BTO Tri-layer Vertically Aligned Nanocomposites

Z. Lin*, Henan Wang*, et al. · Small
* Co-first authors

In preparation

A CeO₂:Au Vertically Aligned Nanocomposite Memristor: From Nonideal Switching Dynamics to Model-Informed Conductance Multilevel Programming

Henan Wang, et al.

Manuscript completed; planned for submission to IEEE EDTM 2027.